Method and apparatus for managing the flow of data within a switching device

ABSTRACT

A method and apparatus for managing the flow of data within a switching device is provided. The switching device includes network interface cards connected to a common backplane. Each interface card is configured to support the maximum transfer rate of the backplane by maintaining a “pending” queue to track data that has been received but for which the appropriate routing destination has not yet been determined. The switching device includes a switch controller that maintains a central card/port-to-address table. When an interface card receives data with a destination address that is not known to the interface card, the interface card performs a direct memory access over a bus that is separate from the backplane to read routing data directly from the central table in the switch controller. Each interface card builds and maintains a routing information table in its own local memory that only includes routing information for the destination addresses that the interface card is most likely to receive.

FIELD OF THE INVENTION

The present invention relates to controlling data flow within a switch,and more specifically, to information distribution and bufferingmechanisms for controlling data flow between multiple network interfacesover a common backplane.

BACKGROUND OF THE INVENTION

Computer networks consist of a plurality of network devices connected ina way that allows the network devices to communicate with each other.Special purpose computer components, such as hubs, routers, bridges andswitches, have been developed to facilitate the process of transportinginformation between network devices.

FIG. 1 is a block diagram of a typical switching device 100. Switchingdevice 100 contains slots for holding network interface cards 102, 104and 106 and a backplane 108 for transporting information between thevarious interface cards 102, 104 and 106. The interface cards 102, 104and 106 have ports that are connected to network devices that arelocated external to switching device 100. For example, port 110 ofinterface card 104 is connected to a network device 112. Port 114 ofnetwork interface card 106 is connected to network devices 116, 118 and120.

Before switching device 100 can accurately route data between devicesconnected to different ports of different cards, switching device 100must know which devices are connected to which ports. Switching device100 obtains this knowledge by inspecting the source addresses associatedwith incoming data.

Typically, incoming data is encapsulated in a structure (e.g. a packetor a cell) that contains both a destination address and a sourceaddress. The destination address identifies the device or group ofdevices to which the data is to be sent. The source address identifiesthe device from which the data is sent. For the purposes of explanation,the term “cell” shall be used herein to refer to any data structure thatcontains data and source/destination information, including but notlimited to Ethernet packets, ATM cells, and token ring packets.

When an interface card receives a cell that specifies a previouslyunknown source address, the interface card stores a port-to-addressentry in a locally-maintained table. The interface card transmits amessage to a central switch controller 122 to notify the switchcontroller 122 that a device with the specified address is connected tothe particular port of the network interface card. Based on theinformation contained in this message, the switch controller 122 adds acard/port-to-address entry in a centrally-maintainedcard/port-to-address table. The card/port-to-address entry indicatesthat the specified port of the interface card that received the cell isconnected to a device that has the source address that was specified inthe cell. When all interface cards on the switching device 100 report tothe switch controller 122 the addresses of the devices to which they areconnected in this fashion, the switch controller 122 is able to createand maintain a relatively complete table that maps addresses to ports oncontroller cards.

As mentioned above, switching device 100 allows network devicesconnected to the ports of one interface card to communicate with networkdevices connected to the ports of other interface cards by allowing thenetwork interface cards to transmit information to each other overbackplane 108. For example, network device 112 can communicate withnetwork device 116 by transmitting data to interface card 104 in a cellthat identifies network device 116 as the desired destination. For thepurposes of explanation, it shall be assumed that the address of networkdevice 116 is ADDRX.

Circuitry on the interface card 104 transmits a message over backplane108 to the switch controller 122 to indicate that the interface card 104has received a cell with the destination address ADDRX. Switchcontroller 122 searches for ADDRX in its card/slot-to-address table todetermine where interface card 104 should send the cell. In the presentexample, the card/slot-to-address table in switch controller 122 wouldcontain an entry to indicate that ADDRX is the address of a deviceconnected to port 114 of interface card 106. The switch controller 122transmits a message containing this information over backplane 108 tointerface card 104.

Based on the information contained in the message, interface card 104routes the cell over the backplane 108 to interface card 106. Interfacecard 106 receives the cell from backplane 108. Upon receiving the cell,interface card 106 transmits a message over backplane 108 to switchcontroller 122 to inform switch controller 122 that interface card 106has received a message with the destination address ADDRX. Switchcontroller 122 transmits a message over backplane 108 to interface card106 to inform interface card 106 that address ADDRX is associated with adevice connected to port 114 of interface card 106. Based on thisinformation, interface card 106 transmits the cell through port 114 todevice 116.

One significant disadvantage of routing cells through switching device100 in the manner described above is that the messages that are sentbetween the switch controller 122 and the various interface cards todetermine the appropriate routing paths are sent over backplane 108.Consequently, less bandwidth is available for transmitting the actualcells between the interface cards.

A second disadvantage to the switching scheme described above is theamount of time that elapses between when an interface card receives acell and the time at which the interface card knows where to send thecell. During this time interval, the interface card may receive a wholeseries of cells for the same destination. To prevent data loss, theinterface card would have to include a much larger buffer than wouldotherwise be required if the interface card could immediately retransmitthe cell.

In an alternate approach, the interface card does not wait for the replyfrom the switch controller 122. Rather, the interface card simplytransmits the cells that it does not know how to route to the switchcontroller 122. The switch controller 122 retransmits the cells to theappropriate destination based on information contained in its table. Theswitch controller also transmits the appropriate routing information tothe interface card so that the interface card will be able to routecells with that destination address in the future.

One disadvantage of this approach is that the same cells are routed overthe backplane twice, increasing the amount of traffic on the backplane.A second disadvantage of this approach is that it places a heavy burdenon the switch controller, because at any given time every interface cardin the switch could be sending cells for the switch controller toreroute.

A third disadvantage is that cells may arrive at their intendeddestination out of sequence. For example, an interface card may receivea series of cells 1..N for an unknown destination. Initially, theinterface card sends the cells to the switch controller. After theinterface card has sent M (where 1<M<N) cells to the switch controller,the interface card receives the reply message from the switch controllerthat indicates how to route the cells. The interface card will thentransmit the remaining cells (M+1)..N directly to the appropriatecard/port. In this scenario, cell M+1 is likely to arrive at thedestination card/port prior to cell M, since cell M is sent to theswitch controller first.

In another alternative approach, each interface card within switchingdevice 100 can locally store a complete card/port-to-address table.According to this approach, each interface card that detects a newsource address will place a message on backplane 108 that indicates thecard and slot on which the message with the new source address wasreceived. Each interface card would read the message off the backplane108 and add the appropriate card/port-to-address entry in its own table.Thus, when an interface card receives a cell, the interface card canquickly determine the appropriate destination for the cell from its owntable without having to send or receive messages over the backplane 108.By reducing the messaging traffic over backplane 108, the throughput ofswitching device 100 is increased. By reducing the delay between receiptof a cell and transmission of the cell, the buffer size within eachinterface card can be reduced.

An approach in which each interface card maintains a completecard/port-to-address table, such as the approach described above, hasthe disadvantage that the table may become very large. Each card wouldhave to reserve large amounts of memory to store the table, and containthe control circuitry for managing a large table. Further, eachinterface card will typically only use a relatively small amount of thedata stored in the table. For example, interface card 104 will neverneed to know the addresses of devices connected to interface card 106that only communicate with other devices connected to interface card106.

Even when a local card/port-to-address table is used by an interfacecard to determine how to route a cell, there is some interval betweenthe time at which the cell is received by the interface card and thetime at which the cell is transmitted by the interface card. During thisinterval, the cell must be stored somewhere within the interface card.FIG. 2 illustrates a typical buffer mechanism 200 that may be employedby interface card 104 to store cells during this interval.

Referring to FIG. 2, it illustrates the buffering circuitry of interfacecard 104 of FIG. 1 in greater detail. Interface card 104 includes afirst-in-first-out (FIFO) buffer 202, a buffer control unit 206 and amain buffer 204. FIFO buffer 202 is coupled between backplane 108 andmain buffer 204. Buffer control unit 206 is coupled to and controls bothFIFO buffer 202 and main buffer 204. In addition to port 110, interfacecard 104 includes ports 208 and 210. Ports 110, 208 and 210 are coupledto main buffer 204.

The main buffer 204 is used to temporarily store both data cells thatare to be transmitted out ports 110, 208 and 210, and data cells thatare to be transmitted to backplane 108. The main buffer 204 includes aplurality of cell slots, each of which is capable of storing one cell ofdata.

Buffer control unit 206 maintains a plurality of queues, including onequeue (212, 214 and 216) for each of ports 110, 208, and 210, a queue220 for backplane 108, and a “free slot” queue 218. Buffer control unit206 stores pointers to the cell slots of main buffer 204 in the variousqueues. Specifically, each cell slot within main buffer 204 has a uniquepointer. The pointer to each cell slot of main buffer 204 is stored inthe queue that corresponds to the destination of the data that iscurrently stored within the cell slot. For example, if a cell slotcurrently stores data to be sent on the backplane 108, then the pointerto the cell slot is stored in the queue 220 that corresponds to thebackplane.

When interface card 104 receives a cell, the interface card 104 mustdetermine the destination of the cell, as described above. Once thedestination of the cell has been determined, buffer control unit 206causes the cell to be stored in main buffer 204 and updates the queuesto reflect that the cell is to be sent to the appropriate destination.

Specifically, when a cell is to be sent out a port, the pointer to thecell slot in which the cell resides is placed in the queue associatedwith the port. When a cell is to be transmitted over the backplane 108,the buffer control unit 206 places the pointer to the cell slot in whichthe cell resides in the queue 220 associated with the backplane 108.

When a cell of data is transmitted by interface card 104, the cell slotthat contained the cell no longer contains data to be transmitted. Toindicate that the cell slot is now available to store incoraing data,the buffer control unit 206 places the pointer to the cell slot in thefree slot queue 218. When storing a cell of data in main buffer 204, thebuffer control unit 206 pulls a pointer from the free slot queue 218,and uses the cell slot indicated by the pointer to store the cell ofdata.

At any given moment all of the other interface cards on backplane 108may be placing cells on backplane 108 that are destined for devicesconnected to interface card 104. To process the cells without losingdata, interface card 104 must be able to sustain, for at least briefperiods of time, a backplane-to-card transfer rate equal to the maximumtransfer rate supported by backplane 108 (e.g. 3.2 gigabytes persecond).

Typically, buffer control unit 206 determines the appropriatedestination for cells at a rate (e.g. 1.2 gigabytes per second) that isslower than the maximum transfer rate of the backplane 108. Therefore,to sustain brief periods in which cells arrive at the high transfer rateof the backplane 108, the information contained on backplane 108 istransferred from the backplane 108 into the high speed FIFO buffer 202of interface card 104. During the interval in which a cell is stored inFIFO buffer 202, interface card 104 determines the destination of thecell. Once the destination of the cell has been determined, buffercontrol unit 206 removes the cell from FIFO buffer 202 and stores thecell in the main buffer 204.

The buffering system illustrated in FIG. 2 has the significantdisadvantage that high speed FIFO buffers are expensive. Further, everyinterface card in the switch must have its own of FIFO buffer to supportthe maximum transfer rate of the backplane. Consequently, the increasedcost of high speed FIFO buffers is incurred for every interface card inthe switch.

Based on the foregoing, it is clearly desirable to provide a switchingdevice in which the delay between when an interface card receives a celland the time at which the interface card transmits the cell is reduced.It is further desirable to provide a switching device in which theamount of traffic on the backplane that is used to determine how toroute cells is reduced. Further, it is desirable to reduce the size andcomplexity of tables that are maintained locally in interface cards. Inaddition, it is desirable to provide a buffering system that allowsinterface cards to receive data off the backplane at the backplane'smaximum transfer rate without requiring the use of high speed FIFObuffers.

SUMMARY OF THE INVENTION

A method and apparatus for managing the flow of data within a switchingdevice is provided. The switching device includes network interfacecards connected to a common backplane. Each interface card is configuredto support the maximum transfer rate of the backplane by maintaining a“pending” queue to track data that has been received but for which theappropriate destination has not yet been determined. The switchingdevice includes a switch controller that maintains a centralcard/port-to-address table. When an interface card receives data with adestination address that is not known to the interface card, theinterface card performs a direct memory access over a bus that isseparate from the backplane to read routing data directly from thecentral table in the switch controller. Each interface card builds andmaintains a routing information table in its own local memory that onlyincludes routing information for the destination addresses that theinterface card is most likely to receive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 is a block diagram of a generic switching device;

FIG. 2 is a block diagram that illustrates the buffering system used ina prior art network interface card;

FIG. 3 is a block diagram that illustrates a buffering system accordingto an embodiment of the present invention; and

FIG. 4 is a block diagram that illustrates a switching device in whichdestination address is distributed to local tables using direct memoryaccess techniques according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Improved BufferMechanism

Referring to FIG. 3, it illustrates the interface card 104 of FIG. 2with a buffer control unit 306 according to an embodiment of the presentinvention. Similar to the buffering mechanism illustrated in FIG. 2,buffer control unit 306 includes a plurality of queues, including queues212, 214, and 216 that correspond to ports 110, 208 and 210, a queue 220that corresponds to the backplane 108, and a free slot queue 218. Inaddition, buffer control unit 306 includes a pending queue 308. As shallbe described hereafter, buffer control unit 306 uses pending queue 308in a way that allows buffer control unit 306. to transfer cells off thebackplane 108 directly into main buffer 204 at the maximum transfer rateof the backplane 108. Consequently, the need for a high speed FIFObuffer is eliminated.

When interface card 104 detects a cell on backplane 108 that is destinedfor interface card 104, an arrival handling unit (AHU) 312 within buffercontrol unit 306 pulls the pointer from the head of free slot queue 218and places the cell directly in the cell slot that corresponds to thepointer. Ideally, the arrival handling unit 312 would then attach thepointer to the tail of the queue that corresponds to the destination ofthe cell. However, as mentioned above, there is not enough time todetermine the destination of a cell before arrival handling unit 312must be available to handle the arrival of a subsequent cell.

Rather than immediately determine the destination of the cell as it isstored in main buffer 204, arrival handling unit 312 simply snoops thedestination address from the cell and places into the pending queue 308both the destination address and the pointer to the cell slot into whichthe cell was placed. Because no destination determination is performedduring this process, arrival handling unit 312 is able to place cellsinto main buffer 204 at the maximum transfer rate of backplane 108.

Buffer control unit 306 includes a route determination unit (RDU) 310that sequentially removes entries from the head of the pending queue 308and determines where cells that have the destination address containedin the entries should be routed. When route determination unit 310determines the proper route for the destination address contained in anentry, the pointer in the entry is placed in the queue that correspondsto the determined route.

Typically, the route determination unit 310 will not be able todetermine the route that corresponds to a destination address in theamount of time that it takes for a subsequent cell to arrive onbackplane 108. Consequently, when cells for interface card 104 arearriving on backplane 108 at the maximum transfer rate of backplane 108,the size of the pending queue will increase. However, in typicalapplications, there will also be periods of relatively low cell arrivalrates. During these periods, route determination unit 310 will beremoving entries from pending queue 308 faster than the arrival handlingunit 312 is adding entries to the pending queue 308.

According to one embodiment, buffer control unit 306 is implemented inan application specific integrated circuit (ASIC). However, manyalternative implementations are possible. For example, the destinationdetermination unit 310 and the arrival handling unit 312 may beimplemented by separate hardwired circuitry, or by programming one ormore processors to perform the described functions. The presentinvention is not limited to any particular implementation of buffercontrol unit 306.

Route Determination Mechanism

The mechanism used by route determination unit 310 to determine theproper route for cells based on the destination address contained withinthe cells significantly affects the cost and efficiency of the switchingdevice in which buffer control unit 306 is used. As mentioned above,interface cards can determine this information by communicating over thebackplane 108 with a switch controller 122 that contains a centralcard/port-to-address table, or by each maintaining their owncard/port-to-address table. However, each of these options hassignificant disadvantages. The approach in which cards send messages torequest the required information from the switch controller 122 isrelatively slow and uses valuable bandwidth on the backplane. Theapproach in which each interface card maintains its own complete tablerequires each card to dedicate a relatively large amount of resourcesfor creating and maintaining the table.

Referring to FIG. 4, it illustrates a switching device 400 configuredaccording to one embodiment of the invention. Switching device 400includes a backplane 428, two interface cards 448 and 402, and a mastercontrol process (MCP) 432. Master control process 432 includes memory450, a memory controller 454, and a processor 452. For the purposes ofexplanation, the master control process 432 is illustrated as anindependent component of switching device 400. However, the mastercontrol process 432 may actually reside on one of the network interfacecards in switching device 400.

Each of the interface cards 402 and 448 includes a plurality of ports, amain buffer, a control unit, a memory controller and a local memory.Specifically, interface card 448 includes three ports 442, 444 and 446,main buffer 418, control unit 420, memory controller 456 and memory 426.Interface card 402 includes three ports 436, 438 and 440, a main buffer404, control unit 406, memory controller 458 and memory 414. The controlunits 420 and 406 generally represent control circuitry which performsvarious control functions, including the functions described above withrespect to buffer control units. Control units 420 and 406 may beimplemented using hard-wired circuitry, a programmed processor, or acombination of hard-wired and programmed circuitry.

In addition to backplane 428, switching device 400 includes a bus 430.Bus 430 is a multiple-line bus (e.g. 16 lines) that interconnects thememory controllers on all of the interface cards and on the memorycontroller in the master control process 432. Bus 430 is separate fromthe path of the normal data flow within switching device 400, whichoccurs over backplane 428. Consequently, the presence of signals on bus430 has no effect on the overall data flow over backplane 428.

Combined Memory Space

Each of memories 426, 450 and 414 is assigned an address space that doesnot overlap with the address space assigned to any other of the memorydevices within switching device 400. For example, memories 426, 450 and414 may be respectively assigned the address spaces 0 to N, (N+1)+M, and(M+1) to L. The address space covered by all of the memories 426, 450and 414 (e.g. 0 to L) is referred to herein as the combined addressspace.

Each of memory controllers 454, 456, and 458 is able to directly performmemory transactions on data stored anywhere within the combined addressspace. An operation that is to be performed on data that is stored inmemory that is not local (with respect to the memory controller thatwill perform the operation) is performed over bus 430. Bus 430 may be,for example, a multiplexed channel in which a memory controller placesan address on the bus 430 during the first half of a clock cycle, andthe memory that includes the memory location specified in the addressplaces the data that resides in the memory location on the bus 430during the second half of a clock cycle.

Because each memory controller is able to perform transfer operations onany data stored within the combined address space, the control units 406and 420 and processor 452 are able to request memory operations to beperformed on any data in the combined address space, regardless of thelocation of the memory that contains the data involved in the operation.Further, according to one embodiment of the invention, each control unitis completely unaware of the address boundaries between the variousmemory devices. The fact that some of the transfer operations are takingplace over bus 430 is completely transparent to the control units 420,406 and processor 452.

For example, control unit 406 may request data to be copied from a firstmemory location to a second memory location. The control unit 406 iscompletely unaware of where the memory device(s) that correspond to thefirst and second memory locations actually reside. For the purposes ofexplanation, it shall be assumed that the first memory location residesin the address space of memory 426, while the second memory locationresides in the address space of memory 414.

To perform the requested operation, control unit 406 simply requestsmemory controller 458 to perform the memory transfer. Memory controller458 retrieves data from the first location by reading the data from theappropriate memory location in memory 426 over bus 430. Memorycontroller 458 then stores the data at the appropriate location inmemory 414.

Direct Access of the Central Table

According to one embodiment of the invention, the centralcard/port-to-address table 434 is stored in the memory 450 of the mastercontrol process 432. The location at which each entry is stored in thetable 434 is determined by performing a hash function on the addressassociated with the entry. The hash function may consist of extractingthe lower N bits from the address, for example. Collisions may beresolved by any one of numerous collision resolution techniques. Thepresent invention is not limited to any particular hash function orcollision resolution technique.

When an interface card receives a cell, the control unit on theinterface card reads the destination address from the cell and performsthe hash function on the destination address. The result of the hashfunction is used as an index into central table 434. The control unittransmits control signals to the memory control unit associated with thecontrol unit, causing the memory control unit to retrieve data from thememory location that corresponds to the index. The memory control unitperforms the transfer operation over bus 430. The control unit uses theretrieved information to determine where to transmit the received cell.

Local Tables

The embodiment described above overcomes many of the disadvantages ofthe prior art. However, the numerous memory accesses that would beperformed over bus 430 in a switching device that has a large number ofinterface cards may exceed the throughput of bus 430. Further, if thecentral table 434 became corrupted or MCP 432 ceased to functionproperly, the entire switching device 400 would cease to function.

To resolve these problems, the interface cards are configured to storein their local memories the portions of the central table 434 in whichthey are most interested. According to one embodiment, each interfacecard maintains its own local table. In the illustrated embodiment,interface card 402 includes a local table 410 stored in memory 414.Interface card 448 includes a local table 422 stored in memory 426.Initially, these tables are empty.

Interface cards add entries to their local tables only as needed. Forexample, assume that interface card 402 receives a cell. The cell isstored in a cell slot of main buffer 404. An entry containing (1) thepointer to the cell slot and (2) the destination address contained inthe cell is placed on the pending queue. When the entry is at the headof the pending queue, the control unit 406 does not immediately invoke amemory operation to retrieve information from the central table 434 inMCP 432. Rather, control unit 406 inspects the local table 410 todetermine whether an entry associated with the destination addressresides in the table 410. If the local table contains an entryassociated with the destination address, then the appropriate routingfor the packet is determined based on the information in the entry ,andthe pointer to the cell slot is placed in the appropriate queue(s).

If the local table 410 does not contain an entry associated with thedestination address contained within the cell, then the control unit 406causes information from the appropriate entry of the central table 434to be retrieved over bus 430 through a direct memory access operation,as described above. The entry from the central table 434 identifies thecard and/or port to which the received cell is to be transmitted. Basedon this information, the control unit 406 places the pointer to the cellslot in which the cell resides in the appropriate queue.

In addition to placing the pointer in the appropriate queue, controlunit 406 generates an entry for table 410 based on the informationretrieved from central table 434. The information stored in the localtable 410 includes information that indicates to where cells thatcontain the destination address in question should be routed. Therefore,when interface card 402 receives cells with the same destination addressin the future, control unit 406 will be able to determine theappropriate routing of the cells without having to access the centraltable 434 stored in the MCP 432.

According to one embodiment of the invention, the entry that correspondsto a given address is stored in the local table at a location based onthe index created by performing a hash function on the address. Theentry for a particular address may contain, for example, the followinginformation: a routing tag, address information, a collision pointer, an“identical address” flag, and aging information.

The routing tag is a tag that indicates the card(s) and port(s) to whichcells with the particular address are to be routed. According to oneembodiment of the invention, the routing tag is a “destination tag”, andeach interface card is configured with a mechanism to route cells to theappropriate cards and ports based on the destination tag. A system thatemploys destination tags to route packets between interface cardsconnected to a common backplane is described in U.S. patent applicationSer. No. 08/501,483 entitled METHOD AND APPARATUS FOR CONTROLLING DATAFLOW WITHIN A SWITCHING DEVICE that was filed on Jul. 12, 1995 byFerguson, the contents of which are incorporated herein by reference.

The address information contained in an entry is information that allowsan interface card to determine the full address that corresponds to theentry. For example, in a system where a portion of the final address isused as an index to the entry, the entry may contain the portion of theaddress that was not used as the index. The full address associated withan entry may therefore be determined based on the location of the entrywithin the local table and the portion of the address that is containedwithin the entry. It may be important to be able to determine the fulladdress associated with an entry in order to resolve collisions when twoaddresses hash to the same index.

The collision pointer is index that points to the memory location of anentry that collided with the current entry. If no collision hasoccurred, then the collision pointer is NULL. The “identical address”flag indicates whether the destination address that corresponds to thisentry is identical to the destination address that corresponds toanother entry.

The aging information indicates how much time has elapsed from thetransmission of the last packet destined to the address. According toone embodiment, the control unit on a card uses the aging information todelete entries that correspond to addresses that have not been used forlonger than some specified amount of time. By deleting entries thatcorrespond to addresses that have not been used for some period of time,the size of the local table is kept to a minimum. If a packet with anaddress that corresponds to an entry arrives after the entry has beendeleted, the interface card must again read information from the centraltable 434 to recreate the entry in the local table.

In the worst case scenario, the operations involved in determining thedestination for a cell include accessing local tables, calculating amemory location, performing a direct memory access to retrieve data fromthe memory location, and updating local tables. None of these operationsrequire the involvement of off-card processors or control units, nor dothey generate any traffic over the backplane. Consequently, even in theworst case, an interface card is able to determine the appropriaterouting of a cell prior to the time at which the interface card mustbegin to process a subsequent cell.

The local table within any given interface card will typically onlycontain a relatively small portion of the information stored in thecentral table 434. Consequently, the amount of resources required ineach interface card to create and maintain the tables is relativelysmall. Further, the information contained in the local memory of aninterface card will be the most relevant information for that particularinterface card.

Using the techniques described above, each interface card graduallybuilds its own local table. If an interface card has already received acell for a particular destination, then the interface card will not haveto perform memory accesses over bus 430 to process subsequent cells forthe same destination. Rather, the interface card will already havestored enough information locally to determine where to send the cellwithout need for further interaction with the master control process432. As a result, the amount of traffic over bus 430 is significantlyreduced.

A second advantage of storing local tables within each interface card isthat the failure of any one component in switching device 400 will notcause the entire switching device 400 to fail. For example, if MCP 432ceases to function properly, then the interface cards may not be able toretrieve destination address from the central table 434. However, theinterface cards will be able to continue to process cells fordestinations for which the interface cards have previously receivedcells.

According to one embodiment, an interface card may access the localtables in other interface cards when the MCP 432 ceases to function.These accesses are performed through the same direct memory accessprocess that interface cards use to read the entries from the centraltable 434. When an interface card finds an entry that corresponds to aparticular address in the local table of another card, the interfacecard copies information from the entry into its own table, just as itdoes when retrieving information from the central table 434.

In the foregoing specification, the invention has been described withreference to specific embodiments thereof. It will, however, be evidentthat various modifications and changes may be made thereto withoutdeparting from the broader spirit and scope of the invention. Thespecification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense.

1-14. (canceled)
 15. A switching device comprising: a master controlprocess including a memory to store routing information; and a pluralityof devices coupled together over a first connection and in communicationwith the master control process, each of the plurality of devicescomprising (i) a local memory including a plurality of entries thatcollectively contain a portion of the routing information stored in thememory of the master control process and (ii) a controller to updatecontents of at least one entry of the local memory from the memory ofthe master control process over a second connection separate from thefirst connection.
 16. The switching device of claim 15, wherein theplurality of devices comprises a first device including a plurality ofports.
 17. The switching device of claim 16, wherein controller of thefirst device updates the contents in response to an event being acondition in which contents of the entry have not been accessed forlonger than a specified amount of time.
 18. The switching device ofclaim 16, wherein the controller of the first device updates thecontents in response to an event being a condition in which a cellhaving a destination address is received and no routing informationassociated with the cell is currently stored in the local memory. 19.The switching device of claim 18, wherein the device further comprisinga control unit that controls the controller in performing a transfer ofthe portion of the routing information from the memory of the mastercontrol process into the local memory.
 20. The switching device of claim18, wherein the cell is a packet including the destination address. 21.The switching device of claim 19, wherein the control unit of the firstdevice further comprising: a buffer; a plurality of queues including apending queue; and an arrival handling unit coupled to the pendingqueue, the arrival handling unit to place a pointer into the pendingqueue, the pointer being associated with a cell slot of the buffer intowhich the cell having the destination address is placed.
 22. Theswitching device of claim 21, wherein the control unit of the firstdevice further comprising a route determination unit that sequentiallyremoves pointers from the pending queue and determines where the cellhaving the destination address should be routed.
 23. The switchingdevice of claim 16, wherein the first device is an interface card. 24.The switching device of claim 19, wherein the controller and the controlunit are implemented as separate circuitry.
 25. A switching devicecomprising: a master control process including a memory to store routinginformation; and a plurality of devices coupled together to exchangedata over a first connection, each of the plurality of devices, being incommunication with the master control process, comprises (i) a localmemory adapted to contain a portion of the routing information stored inthe memory of the master control process and (ii) a controller toreceive the portion of the routing information from the memory of themaster control process over a second connection separate of the firstconnection upon receiving data that includes a destination address aboutwhich no routing information is currently stored in the local memory.26. The switching device of claim 25, wherein the plurality of devicescomprises a first device that comprises (i) a first local memoryincluding a first portion of the routing information stored in thememory of the master control process and (ii) a first controller toreceive the first portion of the routing information from the memory ofthe master control process upon receiving data that includes adestination address about which no routing information is currentlystored in the first local memory; and a second device that comprises (i)a second local memory including a second portion of the routinginformation stored in the memory of the master control process and (ii)a second controller to receive the second portion of the routinginformation from the memory of the master control process upon receivingdata that includes a destination address about which no routinginformation is currently stored in the second local memory.
 27. Theswitching device of claim 26, wherein the second portion of the routinginformation stored in the second local memory differs from the firstportion of the routing information stored in the first local memory. 28.The switching device of claim 25, wherein the portion of the routinginformation is a subset of the routing information stored in the memoryof the master control process.
 29. The switching device of claim 26,wherein the master control process is coupled to each of the pluralityof devices via the second connection being a multiple line bus thatinterconnects the first controller and the second controller.
 30. Theswitching device of claim 25, wherein at least a first device of theplurality of devices further comprises a control unit that controls thecontroller to perform a transfer of the portion of the routinginformation from the memory of the master control process into the localmemory.
 31. The switching device of claim 30, wherein the control unitof the first device further comprising: a buffer; a plurality of queues;and an arrival handling unit coupled to at least one of the plurality ofqueues, the arrival handling unit to place a pointer into an entry ofthe one of the plurality of queues, the pointer being associated with alocation of the buffer into which the data having the destinationaddress is placed.
 32. The switching device of claim 31, wherein thedata is a cell.
 33. The switching device of claim 32, wherein thecontrol unit of the first device further comprising a routedetermination unit that sequentially removes pointers from the one ofthe plurality of queues and determines where the cell having thedestination address should be routed.
 34. The switching device of claim25, wherein the master control process resides separately from theplurality of devices.
 35. The switching device of claim 25, wherein thememory of the master control process stores a card/port-to-address tableto contain the routing information.
 36. The switching device of claim35, wherein the routing information of the card/port-to-address table isindexed by performing a hash operation on at least a portion of thedestination address.
 37. The switching device of claim 35, wherein anaddress space of the memory of the master control process isnon-overlapping with address spaces of the local memories associatedwith the plurality of devices.
 38. The switching device of claim 26,wherein an address space of the memory of the master control process isnon-overlapping with an address space of the first local memoryassociated with the first device and an address space of the secondlocal memory associated with the second device.
 39. The switching deviceof claim 38, wherein the address spaces of the first local memory andthe address space of the second local memory are non-overlapping. 40.The switching device of claim 39, wherein the first controller isadapted to receive routing information contained in the second localmemory of the second device.
 41. The switching device of claim 25,wherein the local memory contains the portion of the routing informationby either (i) reading the portion of the routing information from thememory of the master control process or (ii) writing the portion of therouting information to the local memory.
 42. The switching device ofclaim 35 wherein at least one of the plurality of devices is aninterface card, the first connection being a bus and the secondconnection being a backplane.
 43. A switching device comprising: amemory to store the routing information; and a plurality of componentsin communication with the memory, each of the plurality of componentsincluding a local memory to store a table featuring a portion of therouting information and a memory controller to receive particularrouting information from the memory upon receiving a cell that includesa destination address about which the particular routing information iscurrently not stored.
 44. The switching device of claim 43, wherein theplurality of components are a plurality of interface cards.
 45. Theswitching device of claim 43, wherein the portion of the routinginformation stored in a local memory of a first component of theplurality of components differs from the portion of the routinginformation stored in a local memory of a second component of theplurality of components.
 46. The switching device of claim 43, whereinthe portion of the routing information is a subset of the routinginformation stored in the memory of a master control process.
 47. Theswitching device of claim 43, wherein the cell is a packet including thedestination address.
 48. A switching device comprising: a firstconnection; a second connection; a master control process coupled to thesecond connection, the master control process including a memory tostore routing information; and a first device coupled to the firstconnection and the second connection, the first device comprising alocal memory and a memory controller to read the routing informationfrom the memory of the master control process via the second connectionupon receiving data that includes a destination address about which norouting information is currently stored in the local memory; and asecond device coupled to the first device via the first connection totransfer data to the first device and further coupled to the mastercontrol process via the second connection, the second device comprises alocal memory and a memory controller to read the routing informationfrom the memory of the master control process via the second connectionupon receiving data that includes a destination address about which norouting information is currently stored in the local memory.
 49. Theswitching device of claim 48, wherein the second connection is amultiple line bus that interconnects the memory controller of the firstdevice with the memory controller of the second device.
 50. Theswitching device of claim 48, wherein the memory controller of the firstdevice with the memory controller of the second device exclusively usingthe second connection to read the routing information from the memory ofthe master control process.
 51. A method comprising: exchanging databetween a plurality of components coupled together by a first connectionand collectively forming a switching device; reading routinginformation; inspecting a local table to determine if an entryassociated with the routing information is stored within the localtable; using information from the entry for routing a cell if an entryof the local table associated with the routing information is storedwithin the local table; accessing information from a central table overa second connection separate and independent from the first connectionif no entry associated with the routing information is stored within thelocal table; and receiving the information from the central table foruse in routing the cell having the routing information.
 52. The methodof claim 51 further comprising: storing the information from the centraltable into the local table for subsequent use upon receipt of the cellincluding the routing information.
 53. The method of claim 51, whereinthe cell is a packet including a destination address.
 54. The method ofclaim 53, wherein the reading of the routing information from the cellincludes reading the destination address of the packet.
 55. The methodof claim 53, wherein the inspecting of the local table includesperforming a hashing operation on the destination address of the cell toproduce a result, the result being used as an index for the local table.56. The method of claim 51, wherein the accessing of the informationfrom the central table is conducted by a direct memory access from oneof the plurality of components to a master process control locatedremotely from the one of the plurality of components.
 57. A methodcomprising: receiving a cell over a port coupled to a first memory of afirst device of a switching device, the first device being coupled to asecond device over a first connection to exchange data; reading routinginformation from the cell; inspecting a local table of the first memoryto determine if an entry associated with the routing information isstored within the local table; using information from the entry forrouting the cell if an entry of the local table associated with therouting information is stored within the local table; and populating thelocal table with information accessed from a secondary table stored in asecond memory and retrieved over a second connection different than thefirst connection if no entry associated with the routing information isstored within the local table, the information being used for continuedrouting of the cell.
 58. The method of claim 57, wherein the cell is apacket including a destination address.
 59. The method of claim 58,wherein the inspecting of the local table includes performing a hashingoperation on a destination address of the packet to produce a result,the result being used as an index for the local table.
 60. The method ofclaim 59, wherein the populating of the local table comprisesexclusively using the second connection that is physically separate andindependent from the first connection to route the information from thecentral table to the local table with the first connection being used totransfer information from the cell other than the routing informationbetween the first and second devices of the switching device.
 61. Themethod of claim 57, wherein the populating of the local table includesaccessing an entry of the secondary table of the second memory having anaddress space non-overlapping with an address space assigned to thefirst memory using a direct memory access operation.
 62. A methodcomprising: storing data from a first connection into a location withina buffer; snooping address information from the data detected on thefirst connection; placing the address information and a pointer to thelocation into an entry of a queue; determining a routing destinationbased on the address information; and transmitting the data from thelocation within the buffer of the device based on the routinginformation.